Abstract— paper a new power gating technique

Abstract—
In many VLSI chips, Static Random Access memory (SRAM) has become an important
component due to their large storage capacity and small access time. Low power
adequate memory design is one of the most challenging issues in SRAM
architecture. As the technology node scaling down, leakage power consumption
has become a significant problem. There are various power gating schemes available
in the literature such as sleep technique, stack technique, sleepy stack
technique, sleepy keeper technique, lector technique, foot switch technique and
double switch technique for leakage power reduction. In this paper a new power
gating technique namely sleepy keeper leakage control transistor technique
(SK-LCT) is proposed for a low power SRAM architecture design. The SRAM
architecture has two main components namely SRAM cell and sense amplifier. The
proposed SK-LCT technique is applied in both SRAM cell and sense amplifier for
a new low power high speed SRAM architecture design. Simulation is done using
Tanner EDA tool in 180nm technology and the results obtained shows a
significant improvement in leakage power consumption and speed.

 

Index Terms— SRAM,
SK-LCT Technique, Tanner EDA

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          I.  INTRODUCTION

             Very Large Scale Integration is
the process of creating an Integrated Circuit by combining thousand of
transistors in a single chip. Rapid growth in VLSI fabrication process results
in the increase of the densities of integrated circuit by scaling down the
technology1. With the advancement in technology that are happening in the
world, the demand for large storage of data is increasing in a way that needs
to be  faster  than   the
existing technologies2.Simultaneously,
increase of power dissipation has become the 
  major obstacle against further development of
VLSI circuits. Power consumption due to memory accesses in a computing system,
often constitutes a dominant portion of the total power consumption 3.

             Static Random Access
Memory (SRAM) is an important part of most of the digital chips
which consumes  a  large percent of  power of  each  chip,
so

 

decreasing the power
of SRAM can lead to a decrease in the overall power of chips. Due to quadratic
relation between power and supply voltage of transistors 4, one effective and
common method to reduce the power consumption is to decrease the supply
voltage. Due to the strong
demand of the SRAM memory  in mobile
products, System On-Chip (SoC) & high performance VLSI circuits, the
reduction of power consumption is very important. In addition, the leakage
power consumption of the SRAM during WRITE operation is high because of the
high bit-line swing requirement. To overcome this problem, several methods have
been proposed. There
are various power gating schemes available in the literature such as sleep
technique, stack technique, sleepy stack technique, sleepy keeper technique, LECTOR
technique, foot switch technique and double switch technique for leakage power
reduction.

              A
novel power gating technique namely SK-LCT Technique is used in the design of
SRAM cell and sense amplifier. The SRAM architecture using SK-LCT technique has
several advantages over the conventional SRAMs design like improved read and
write ability which are achieved with a higher read speed and less energy
consumption.

II. POWER GATING
TECHNIQUES

             Power
gating is a technique used in integrated circuit design to reduce power
consumption, by shutting off the current to blocks of the circuit which are not
in use. In addition to reducing standby or leakage power, power gating has the
benefit of enabling Iddq testing. An externally switched power supply is a very
basic form of power gating to achieve long term leakage power reduction.

1.       
POWER GATING IN  SRAM CELL

             During standby mode, most of the power is
wasted in SRAM cell; because leakage power plays a predominant role in SRAM
power consumption. Here, some of the Power gating techniques used to reduce the
leakage power of SRAM cell.

A.      
Sleep Technique

            In the sleep technique, (i) an additional
“sleep S” PMOS transistor is placed between VDD and pull up network of a
circuit and (ii) an additional “sleep S BAR” NMOS transistor is placed between
the pull down network and ground as shown in Fig.1.

            During stand-by mode both sleep transistors
gets turned off which introducing large resistance in conduction path and thus
reduce the leakage current. Isolation between VDD and ground path is necessary
for leakage reduction. This technique faces a problem for data retention purpose
during sleep mode. The wake up time and energy of the sleep technique has a
significant impact on the efficiency of the circuit5.

Fig.1: Sleep
Technique

B.      
Stack Technique

             The stack approach forces a stack effect by
breaking down an existing transistor into two half size transistors as shown in
Fig.2. When the two transistors are turned off together, it induces a reverse
bias between the two transistors which results in sub threshold leakage current
reduction.

Fig.2:
Stack Technique

              However, divided transistor increases delay
significantly and could limit the usefulness of the approach6.When both the
transistors are turned off, sub threshold leakage current is reduced. It is
state retention technique with disadvantage of increased delay and area7.

C.     
Sleepy stack Technique

            Sleepy
Stack technique combines the features of sleepy transistor technique and forced
stack technique as shown in Fig.3.

Fig.3: Sleepy
stack Technique

            In
this technique, the sleep transistor is added parallel to the two half sized
transistors configuration and it also replace the original transistor of the
circuit. During sleep mode, sleep transistors are turned off and stacked
transistors suppress leakage current while saving state.  Variation in the width of sleep transistor
results tradeoff in power, area and delay. This approach requires control and
monitoring circuit is required for the sleep transistor had been mentioned. The
sleepy stack technique can utilize high-Vth transistors without delay penalties
8.

D.     
Sleepy keeper Technique

              A new approach called sleepy keeper formed by
the combined effect of sleep and stack keeper approach to reduce the leakage
power by using additional transistors with pull-up and pull-down network 8.

Fig.4:
Sleepy keeper Technique

              In Sleepy Keeper Technique parallel connected
combination of PMOS and NMOS transistor is inserted between pull up network
& VDD and pull down network &GND. The basic structure of sleepy keeper
is shown in Fig.4. In sleep mode, this additional transistor is the only source
of VDD to the pull up network and pull down network .To maintain output value 1
in sleep mode, this approach uses pre-estimated output logic1 and NMOS
transistor connected to VDD and vice versa. Thus, sleepy keeper resulted in
stable states with minimum static power consumption.

E.      
LECTOR Technique

           In this technique two leakage control
transistors i.e. P-type and N-type are inserted between the pull up and pull
down network of a circuit as shown in Fig.5.

Fig.5:
LECTOR Technique

              Here, gate is controlled by the
source of the other, hence termed as self controlled stack transistor which is
required for controlling purpose. Since it is a self controlled technique so no
external circuit is needed. These gates produce high resistance path between
the VDD and GND by turning more than one transistor OFF, thereby reducing
leakage current. This technique has a very low leakage power which results in
delay penalty 9.Data Retention problem occurs in the circuit, which can be reduced
by inserting sleep transistor along with pull up and pull down network10.Abstract—
In many VLSI chips, Static Random Access memory (SRAM) has become an important
component due to their large storage capacity and small access time. Low power
adequate memory design is one of the most challenging issues in SRAM
architecture. As the technology node scaling down, leakage power consumption
has become a significant problem. There are various power gating schemes available
in the literature such as sleep technique, stack technique, sleepy stack
technique, sleepy keeper technique, lector technique, foot switch technique and
double switch technique for leakage power reduction. In this paper a new power
gating technique namely sleepy keeper leakage control transistor technique
(SK-LCT) is proposed for a low power SRAM architecture design. The SRAM
architecture has two main components namely SRAM cell and sense amplifier. The
proposed SK-LCT technique is applied in both SRAM cell and sense amplifier for
a new low power high speed SRAM architecture design. Simulation is done using
Tanner EDA tool in 180nm technology and the results obtained shows a
significant improvement in leakage power consumption and speed.

 

Index Terms— SRAM,
SK-LCT Technique, Tanner EDA

 

 

          I.  INTRODUCTION

             Very Large Scale Integration is
the process of creating an Integrated Circuit by combining thousand of
transistors in a single chip. Rapid growth in VLSI fabrication process results
in the increase of the densities of integrated circuit by scaling down the
technology1. With the advancement in technology that are happening in the
world, the demand for large storage of data is increasing in a way that needs
to be  faster  than   the
existing technologies2.Simultaneously,
increase of power dissipation has become the 
  major obstacle against further development of
VLSI circuits. Power consumption due to memory accesses in a computing system,
often constitutes a dominant portion of the total power consumption 3.

             Static Random Access
Memory (SRAM) is an important part of most of the digital chips
which consumes  a  large percent of  power of  each  chip,
so

 

decreasing the power
of SRAM can lead to a decrease in the overall power of chips. Due to quadratic
relation between power and supply voltage of transistors 4, one effective and
common method to reduce the power consumption is to decrease the supply
voltage. Due to the strong
demand of the SRAM memory  in mobile
products, System On-Chip (SoC) & high performance VLSI circuits, the
reduction of power consumption is very important. In addition, the leakage
power consumption of the SRAM during WRITE operation is high because of the
high bit-line swing requirement. To overcome this problem, several methods have
been proposed. There
are various power gating schemes available in the literature such as sleep
technique, stack technique, sleepy stack technique, sleepy keeper technique, LECTOR
technique, foot switch technique and double switch technique for leakage power
reduction.

              A
novel power gating technique namely SK-LCT Technique is used in the design of
SRAM cell and sense amplifier. The SRAM architecture using SK-LCT technique has
several advantages over the conventional SRAMs design like improved read and
write ability which are achieved with a higher read speed and less energy
consumption.

II. POWER GATING
TECHNIQUES

             Power
gating is a technique used in integrated circuit design to reduce power
consumption, by shutting off the current to blocks of the circuit which are not
in use. In addition to reducing standby or leakage power, power gating has the
benefit of enabling Iddq testing. An externally switched power supply is a very
basic form of power gating to achieve long term leakage power reduction.

1.       
POWER GATING IN  SRAM CELL

             During standby mode, most of the power is
wasted in SRAM cell; because leakage power plays a predominant role in SRAM
power consumption. Here, some of the Power gating techniques used to reduce the
leakage power of SRAM cell.

A.      
Sleep Technique

            In the sleep technique, (i) an additional
“sleep S” PMOS transistor is placed between VDD and pull up network of a
circuit and (ii) an additional “sleep S BAR” NMOS transistor is placed between
the pull down network and ground as shown in Fig.1.

            During stand-by mode both sleep transistors
gets turned off which introducing large resistance in conduction path and thus
reduce the leakage current. Isolation between VDD and ground path is necessary
for leakage reduction. This technique faces a problem for data retention purpose
during sleep mode. The wake up time and energy of the sleep technique has a
significant impact on the efficiency of the circuit5.

Fig.1: Sleep
Technique

B.      
Stack Technique

             The stack approach forces a stack effect by
breaking down an existing transistor into two half size transistors as shown in
Fig.2. When the two transistors are turned off together, it induces a reverse
bias between the two transistors which results in sub threshold leakage current
reduction.

Fig.2:
Stack Technique

              However, divided transistor increases delay
significantly and could limit the usefulness of the approach6.When both the
transistors are turned off, sub threshold leakage current is reduced. It is
state retention technique with disadvantage of increased delay and area7.

C.     
Sleepy stack Technique

            Sleepy
Stack technique combines the features of sleepy transistor technique and forced
stack technique as shown in Fig.3.

Fig.3: Sleepy
stack Technique

            In
this technique, the sleep transistor is added parallel to the two half sized
transistors configuration and it also replace the original transistor of the
circuit. During sleep mode, sleep transistors are turned off and stacked
transistors suppress leakage current while saving state.  Variation in the width of sleep transistor
results tradeoff in power, area and delay. This approach requires control and
monitoring circuit is required for the sleep transistor had been mentioned. The
sleepy stack technique can utilize high-Vth transistors without delay penalties
8.

D.     
Sleepy keeper Technique

              A new approach called sleepy keeper formed by
the combined effect of sleep and stack keeper approach to reduce the leakage
power by using additional transistors with pull-up and pull-down network 8.

Fig.4:
Sleepy keeper Technique

              In Sleepy Keeper Technique parallel connected
combination of PMOS and NMOS transistor is inserted between pull up network
& VDD and pull down network &GND. The basic structure of sleepy keeper
is shown in Fig.4. In sleep mode, this additional transistor is the only source
of VDD to the pull up network and pull down network .To maintain output value 1
in sleep mode, this approach uses pre-estimated output logic1 and NMOS
transistor connected to VDD and vice versa. Thus, sleepy keeper resulted in
stable states with minimum static power consumption.

E.      
LECTOR Technique

           In this technique two leakage control
transistors i.e. P-type and N-type are inserted between the pull up and pull
down network of a circuit as shown in Fig.5.

Fig.5:
LECTOR Technique

              Here, gate is controlled by the
source of the other, hence termed as self controlled stack transistor which is
required for controlling purpose. Since it is a self controlled technique so no
external circuit is needed. These gates produce high resistance path between
the VDD and GND by turning more than one transistor OFF, thereby reducing
leakage current. This technique has a very low leakage power which results in
delay penalty 9.Data Retention problem occurs in the circuit, which can be reduced
by inserting sleep transistor along with pull up and pull down network10.